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DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache

Jinbo Chen 1 Keren Liu 1 Xiaochen Guo 2 Patrick Girard 3 Yuanqing Cheng 1
3 IDH - Interactive Digital Humans
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : As device integration density increases exponentially predicted by Moore's law, power consumption becomes a bottleneck for system scaling. On the other hand, leakage power of on-chip cache occupies a large fraction of the total power budget. STT-RAM is a promising candidate to replace SRAM as on-chip cache due to its ultra-low leakage power, high integration density and non-volatility. However, building L1 cache with STT-RAM still faces severe challenges especially because of its high write latency and energy overheads. Moreover, intensive accesses in L1 cache accelerate oxide breakdown and threaten the lifetime of STT-RAM significantly. In this paper, we propose a Dynamic Overwriting Voltage Adjustment (DOVA) technique for STT-RAM L1 cache. A high write voltage is used for performance critical cache lines while a low write voltage is used for other cache lines to approach an optimal trade-off between reliability and performance. Experimental results show that the proposed technique can improve cache performance up to 18%, and 9% on average with almost the same reliability level as in the case when only the low write voltage is used.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03035589
Contributor : Isabelle Gouat <>
Submitted on : Wednesday, December 2, 2020 - 11:45:10 AM
Last modification on : Thursday, December 3, 2020 - 3:22:12 AM
Long-term archiving on: : Wednesday, March 3, 2021 - 7:02:48 PM

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Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng. DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. 21st International Symposium on Quality Electronic Design (ISQED), Mar 2020, Santa Clara, CA, United States. pp.408-414, ⟨10.1109/ISQED48828.2020.9137020⟩. ⟨lirmm-03035589⟩

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