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Conference papers

Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation

Quentin Huppert 1 Timon Evenblij 2 Manu Perumkunnil 2 Francky Catthoor 2 Lionel Torres 1 David Novo 1 
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Computer system simulators are major tools used by architecture researchers. Two key elements play a role in the credibility of simulator results: (1) the simulator's accuracy, and (2) the quality of the baseline architecture. Some simulators, such as gem5, already provide highly accurate parameterized models. However, finding the right values for all these parameters to faithfully model a real architecture is still a problem. In this paper, we calibrate the memory hierarchy of an in-order core gem5 simulation to accurately model a real mobile Arm SoC. We execute small programs, which we design to stress specific parts of the memory system, to deduce key parameter values for the model. We compare the execution of SPEC CPU2006 benchmarks on the real hardware with the gem5 simulation. Our results show that our calibration reduces the average and worst-case IPC error by 36% and 50%, respectively, when compared with a gem5 simulation configured with the default parameters.
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Submitted on : Monday, December 21, 2020 - 9:49:10 AM
Last modification on : Tuesday, July 5, 2022 - 10:30:34 AM




Quentin Huppert, Timon Evenblij, Manu Perumkunnil, Francky Catthoor, Lionel Torres, et al.. Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation. DATE 2021 - 24th Design, Automation and Test in Europe Conference and Exhibition, Feb 2021, Grenoble (Virtual), France. pp.707-710, ⟨10.23919/DATE51398.2021.9474108⟩. ⟨lirmm-03084343⟩



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