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Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing

Guillaume Devic 1 Maxime France Pillois 1 Jérémie Salles 1 Gilles Sassatelli 1 Abdoulaye Gamatié 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Machine learning algorithms are compute-and memory-intensive. Their execution at the edge on resourceconstrained embedded systems is challenging. Data quantization, i.e. data bit-width reduction, contributes to reducing de-facto the memory bandwidth requirement. In order to best exploit this bit-width reduction, a prevailing approach consists of tailored hardware accelerators. Another approach relies on generalpurpose compute units with Single Instruction Multiple Data (SIMD) support for reduced data bit-width precision, as in ARM Cortex-M [1] or RISC-V based RI5CY [2] processors. However, such processors only handle a few predefined bit-width ranges, e.g. 8-bit and 16-bit only for the ARM SIMD. This paper proposes a flexible architecture of Multiply-and-Accumulate (MAC) unit allowing asymmetric multiplication for operand sizes in powers of 2, up to 32 bits. The synthesis of this architecture in 28nm FD-SOI technology shows 10% and 25% reduction in area and dynamic power respectively, compared to the RI5CY MAC unit. From the energy-efficiency point of view, up to 50% improvements are achieved.
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Contributor : Guillaume Devic <>
Submitted on : Friday, May 28, 2021 - 6:35:24 PM
Last modification on : Wednesday, September 1, 2021 - 3:06:14 PM
Long-term archiving on: : Sunday, August 29, 2021 - 7:47:59 PM


NEWCAS_2021_Highly-Adaptive Mi...
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  • HAL Id : lirmm-03241639, version 1



Guillaume Devic, Maxime France Pillois, Jérémie Salles, Gilles Sassatelli, Abdoulaye Gamatié. Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing. 19th IEEE Interregional NEWCAS Conference (NEWCAS 2021), Jun 2021, Toulon (virtual), France. ⟨lirmm-03241639⟩



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