Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Preprints, Working Papers, ... Year : 2021

Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC

Pierre-Yves Péneau
David Novo
Florent Bruguier
Lionel Torres
Gilles Sassatelli
Abdoulaye Gamatié

Abstract

Modern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance and energy. Well-known benefits of STT-MRAM are their near-zero static power and high density compared to volatile memories. Nonetheless, their high write latency may be detrimental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache replacement policy. The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up to 10% and 14% compared to SRAM cache with LRU respectively on single and multicore systems. Moreover, the energy consumption is on average decreased by 20% for all platforms.
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Dates and versions

lirmm-03341604 , version 1 (11-09-2021)

Identifiers

  • HAL Id : lirmm-03341604 , version 1

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Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, et al.. Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC. 2021. ⟨lirmm-03341604⟩
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