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On Preventing SAT Attack with Decoy Key-Inputs

Quang-Linh Nguyen 1 Marie-Lise Flottes 1 Sophie Dupuis 1 Bruno Rouzeyre 1 
1 TEST - Test and dEpendability of microelectronic integrated SysTems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The globalized supply chain in the semiconductor industry raises several security concerns such as IC overproduction, intellectual property piracy and design tampering. Logic locking has emerged as a Design-for-Trust countermeasure to address these issues. Original logic locking proposals provide a high degree of output corruption-i.e., errors on circuit outputsunless it is unlocked with the correct key. This is a prerequisite for making a manufactured circuit unusable without the designer's intervention. Since the introduction of SAT-based attacks-highly efficient attacks for retrieving the correct key from an oracle and the corresponding locked design-resulting design-based countermeasures have compromised output corruption for the benefit of better resilience against such attacks. Our proposed logic locking scheme, referred to as SKG-Lock, aims to thwart SAT-based attacks while maintaining significant output corruption. The proposed provable SAT-resilience scheme is based on the novel concept of decoy key-inputs. Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03359458
Contributor : Sophie Dupuis Connect in order to contact the contributor
Submitted on : Thursday, September 30, 2021 - 11:11:10 AM
Last modification on : Friday, August 5, 2022 - 3:03:29 PM
Long-term archiving on: : Friday, December 31, 2021 - 7:23:24 PM

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Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI 2021 - IEEE Computer Society Annual Symposium on VLSI, Jul 2021, Tampa, United States. pp.114-119, ⟨10.1109/ISVLSI51109.2021.00031⟩. ⟨lirmm-03359458⟩

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