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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Aibin Yan 1 Zhihui He 1 Jun Zhou 1 Jie Cui 1 Tianming Ni 2 Zhengfeng Huang 1 Xiaoqing Wen 3 Patrick Girard 4
4 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03380265
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Submitted on : Friday, October 15, 2021 - 1:50:57 PM
Last modification on : Friday, October 22, 2021 - 3:07:43 PM

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Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, et al.. Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectronics Journal, Elsevier, 2021, 111, pp.#105034. ⟨10.1016/j.mejo.2021.105034⟩. ⟨lirmm-03380265⟩

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