Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles IEEE Transactions on Very Large Scale Integration (VLSI) Systems Year : 2022

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization

Rongmei Chen
Lin Chen
  • Function : Author
Jie Liang
  • Function : Author
Yuanqing Cheng
Jaehyun Lee
Kangwei Xu
  • Function : Author
Peter Debacker
  • Function : Author
Aida Todri-Sanial

Abstract

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on the tradeoff between performance, stability, and power efficiency. In addition to size optimization, physical model parameters including CNT density, CNT diameter, and CNFET flat band voltage are evaluated and optimized for CNFET SRAM performance improvement. Optimized CNFET SRAM is compared with state-of-the-art 7-nm FinFET SRAM cell based on Arizona State University [ASAP 7-nm FinFET predictive technology models (PTM)] library. We find that the read, write EDPs, and static power of the proposed CNFET SRAM cell are improved by 67.6%, 71.5%, and 43.6%, respectively, compared with the FinFET SRAM cell, with slightly better stability. CNT interconnects both inside and in-between CNFET SRAM cells are considered to compose an all-carbon-based SRAM (ACS) array which will be discussed in the Part II of this article. A 7-nm FinFET SRAM cell with copper interconnects is implemented and used for comparison.
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Dates and versions

lirmm-03593054 , version 1 (28-09-2023)

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Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, et al.. Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30 (4), pp.432-439. ⟨10.1109/TVLSI.2022.3146125⟩. ⟨lirmm-03593054⟩
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