As the semiconductor industry continues to shrink the transistor feature size, new fault models need to be invented and deployed to ensure manufacturing test and diagnostic of the highest quality. The Cell-Aware (CA) test and diagnosis methodology targets the detection of defects inside standard (std) cells, at the transistor level. While becoming an industry standard, the CA methodology, has a large and costly deployment overhead, involving numerous analog simulations. In [1], we presented an innovative flow using Machine-Learning (ML) to reduce the CA test method runtime and ease its adoption for industrial usage. Experiments using different technology nodes demonstrated an over 99% runtime reduction for 80% of combinational cells. In this paper, new elements are presented to more widely take advantage of the ML flow for CA characterization. This includes a new decision algorithm, leveraging ML techniques to decide whether the CA characterization of a new std cell should be ML-based or simulation-based, thus allowing to decrease the CA characterization runtime while maintaining high quality CA models for all cells. Experimental results demonstrate the high performance of the new decision algorithm. The fault coverage on real cell-internal defects of ATPG patterns using ML predicted CA data proves that our predicted CA data can accurately replace those obtained by running extensive analog simulations, thus proving the effectiveness and pertinence of the proposed methodology.