On Using Cell-Aware Models for Representing SRAM Architecture
Abstract
This paper presents a novel approach to memory testing which relies on Cell-Aware (CA) test to further improve the yield in SoCs. Therefore, using CA test shifts the memory testing methodology from functional to structural testing. In this paper, a 4 by 4 SRAM architecture is used as a case study. Through transistor to gate-level transformation, the SRAM is represented as an ensemble of "special" standard cells on which the CA test can then be applied.
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