Non-Volatile Latch Designs with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Journal Articles IEEE Transactions on Very Large Scale Integration (VLSI) Systems Year : 2024

Non-Volatile Latch Designs with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS

Aibin Yan
Litao Wang
  • Function : Author
  • PersonId : 1293776
Jie Cui
Zhengfeng Huang
Tianming Ni
Xiaoqing Wen

Abstract

As semiconductor technologies scale down, radiativeparticle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunneljunctions (MTJs) are widely used to address these concerns. MTJs are non-volatile and compatible with traditional CMOS processes. In this paper, we first propose a double-node-upset (DNU) tolerant and non-volatile latch, i.e., M-TPDICE-V2, providing high reliability. Additionally, we further propose an advanced latch, namely M-8C, that is able to completely recover from single-nodeupsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing non-volatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. MTPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.
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Dates and versions

lirmm-04239391 , version 1 (12-10-2023)

Identifiers

Cite

Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, et al.. Non-Volatile Latch Designs with Node-Upset Tolerance and Recovery using Magnetic Tunnel Junctions and CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32 (1), pp.116-127. ⟨10.1109/TVLSI.2023.3323562⟩. ⟨lirmm-04239391⟩
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