High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2023

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology

Aibin Yan
Zhen Zhou
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  • PersonId : 1161770
Liang Ding
  • Function : Author
  • PersonId : 1113641
Jie Cui
Zhengfeng Huang
Xiaoqing Wen

Abstract

With the advancement of CMOS technologies, circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). To effectively provide nonvolatility as well as tolerance against DNUs caused by radiation, this paper proposes a nonvolatile and DNU resilient latch that mainly comprises two magnetic tunnel junction (MTJ), two inverters and eight C-elements. Since two MTJs are used and all internal nodes are interlocked, the latch can provide nonvolatility and recovery from all possible DNUs. Simulation results demonstrate the nonvolatility, DNU recovery and high performance of the proposed latch.
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Dates and versions

lirmm-04240330 , version 1 (13-10-2023)

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Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, et al.. High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. DATE 2023 - Design, Automation & Test in Europe Conference & Exhibition, Apr 2023, Antwerp, Belgium. ⟨10.23919/DATE56975.2023.10136927⟩. ⟨lirmm-04240330⟩
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