Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2023

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications

Aibin Yan
Jing Xiang
  • Function : Author
  • PersonId : 1161846
Zhengfeng Huang
Tianming Ni
Jie Cui
Xiaoqing Wen

Abstract

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and lowpower SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recover from DNUs. Simulationbased evaluation results demonstrate advantages in terms of delay and power consumption over epical existing SRAM cell designs.
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Dates and versions

lirmm-04241173 , version 1 (13-10-2023)

Identifiers

  • HAL Id : lirmm-04241173 , version 1

Cite

Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, et al.. Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. ITC-Asia 2023 - IEEE International Test Conference in Asian, Sep 2023, Matsue, Japan. ⟨lirmm-04241173⟩
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