Memory components are increasingly used in modern systems such as System-on-Chip (SoC). Moreover, they are becoming more complex as the technology node shrinks, which makes them more prone to manufacturing defects. A large part of memory testing is based on functional tests, using March algorithms to target Functional Fault Models (FFMs). New test methodologies are developed to anticipate the growing complexity of memory components, such as the Cell-Aware (CA) test methodology which has been recently introduced in the field of memory testing. However, in order to apply the CA methodology, which introduces a structural consideration of the circuit to be tested, an accurate digital model of the SRAM has to be designed. This paper proposes a methodology to produce a digital Verilog-HDL netlist of an SRAM, based on an initial analog model (SPICE netlist). The resulting digital model considers the bidirectional nature of the memory, and it is ATPG-compliant, allowing test patterns generation and fault simulation as well.