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Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Abstract : This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 μm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00105313
Contributor : Christine Carvalho de Matos <>
Submitted on : Wednesday, October 11, 2006 - 7:51:23 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 7:17:36 PM

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Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. Journal of Electronic Testing, Springer Verlag, 2005, 21 (2), pp.169-179. ⟨10.1007/s10836-005-6146-1⟩. ⟨lirmm-00105313⟩

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