In this paper we show the influence of inductance and routing orientation on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and the other with the drivers in opposite directions. For a typical DSM (deep-sub-micron) process, we show that when analyzing VLSI circuits, if standard distributed RC models are used, and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the circuit behavior. Both greatly affect circuit performances: the discrepancy rates can reach 20% and 18% respectively for the latency and 50% and 30% for the output switching delay. The routing orientation can lead to a difference of 18% for the latency and 35% for the output transition time when the two lines have the same transitions.