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Conference papers

Automatic Layout Synthesis Based Performance Optimization

Alexis Landrault 1 Nadine Azemard 2 Philippe Maurine 2 Michel Robert 2 Daniel Auvergne 1
1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108654
Contributor : Christine Carvalho de Matos Connect in order to contact the contributor
Submitted on : Monday, October 23, 2006 - 8:52:40 AM
Last modification on : Monday, October 11, 2021 - 1:24:09 PM

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  • HAL Id : lirmm-00108654, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Alexis Landrault, Nadine Azemard, Philippe Maurine, Michel Robert, Daniel Auvergne. Automatic Layout Synthesis Based Performance Optimization. IWLS: International Workshop on Logic Synthesis, Jun 2004, Temecula, CA, United States. pp.80-85. ⟨lirmm-00108654⟩

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