Some Optimizations of Hardware Multiplication by Constant Matrices

Nicolas Boullis 1 Arnaud Tisserand 1, 2
2 ARITH - Arithmétique informatique
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.
Type de document :
Article dans une revue
IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2005, 54 (10), pp.1271-1282. 〈10.1109/TC.2005.168〉
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Soumis le : vendredi 10 novembre 2006 - 15:31:42
Dernière modification le : jeudi 24 mai 2018 - 15:59:21
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Nicolas Boullis, Arnaud Tisserand. Some Optimizations of Hardware Multiplication by Constant Matrices. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2005, 54 (10), pp.1271-1282. 〈10.1109/TC.2005.168〉. 〈lirmm-00113092〉

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