An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2006

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lirmm-00135456 , version 1 (07-03-2007)

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Patrick Girard, Serge Pravossoudovitch, Olivier Héron, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. Journal of Electronic Testing: : Theory and Applications, 2006, 22 (2), pp.161-172. ⟨10.1007/s10836-005-4631-1⟩. ⟨lirmm-00135456⟩
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