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An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Keywords : FPGA BIST Delay Testing
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00135456
Contributor : Christian Landrault <>
Submitted on : Wednesday, March 7, 2007 - 4:50:30 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00135456, version 1

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Patrick Girard, Serge Pravossoudovitch, Olivier Héron, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. Journal of Electronic Testing, Springer Verlag, 2006, 22 (2), pp.161-172. ⟨lirmm-00135456⟩

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