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Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis

Luigi Dilillo 1 Bashir Al-Hashimi 2 Paul Rosinger 2 Patrick Girard 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we study the impact of leakage currents that strongly affect the operation of SRAM memories fabricated using nanoscale technologies. We show how the leakage currents, flowing through the pass transistors of unselected cells, may affect the read operation. A new fault model, named Leakage Read Fault (LRF), is introduced and the results of extensive Spice simulation on a 65nm SRAM are analyzed to evaluate the occurrence of the LRF for different operating conditions including supply voltage, temperature and frequency. Furthermore, the test requirements to cover LRFs are given and a low complexity (2N) March test is proposed for diagnostic purposes.
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Contributor : Patrick Girard <>
Submitted on : Tuesday, March 20, 2007 - 5:07:52 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM


  • HAL Id : lirmm-00137603, version 1



Luigi Dilillo, Bashir Al-Hashimi, Paul Rosinger, Patrick Girard. Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis. IDT'06: IEEE International Design and Test Workshop, Nov 2006, Dubai, United Arab Emirates. pp.110-115. ⟨lirmm-00137603⟩



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