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A Novel Parity Bit Scheme for SBOX in AES Circuits

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00141799
Contributor : Marie-Lise Flottes <>
Submitted on : Monday, April 16, 2007 - 11:08:31 AM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Wednesday, April 7, 2010 - 1:09:31 AM

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  • HAL Id : lirmm-00141799, version 1

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. DDECS'07: Design and Diagnostics of Electronic Cicruits and Systems, Apr 2007, Cracovie, Pologne, pp.267-271. ⟨lirmm-00141799⟩

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