A Novel Parity Bit Scheme for SBOX in AES Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2007

A Novel Parity Bit Scheme for SBOX in AES Circuits

Abstract

This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.
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Dates and versions

lirmm-00141799 , version 1 (16-04-2007)

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2007, Cracovie, Poland. pp.267-271, ⟨10.1109/DDECS.2007.4295295⟩. ⟨lirmm-00141799⟩
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