Scan technology increases the switching activity well beyond that of the functional operation of an IC. In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (i.e. between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process. The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm. Experimental evidence and practical implications of the proposed solution are given at the end of the paper. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool. Fault coverage and test time are left unchanged by the proposed solution.