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Book Sections Year : 2007

SIP Test Architectures


Over the past two decades, we have seen the emergence and rapid growth of system-on-chip (SOC) applications. The same trend has happened in system-in-package (SIP) applications over the past ten years. The development of the SIP technology has much benefited from the SOC technology; however, this emerging SIP technology presents very specific test challenges due to its complex design and test processes. Indeed, one major difference between an SOC and an SIP is that an SOC contains only one die on a packaged chip while an SIP is an assembled system comprised of individual dies on a packaged chip. Each die in the SIP can also use different process technology, such as silicon or GaAs, which includes a radiofrequency (RF) or micro-electromechanical system (MEMS) component. This fundamental difference implies that to test an SIP, each bare die in the SIP must be tested first before the passing bare die is packaged in the SIP. Then, a functional system test or embedded component test at the system level can be performed. The passing bare dies are often called known-good-die (KGD). In this chapter, we first discuss the basic SIP concepts, its difference from SOC, and show some SIP examples. We highlight the specific challenges from the testing point of view and derive the assembled yield and defect level for the packaged SIP. Next, various bare-die test techniques to find known-good-dies are described including their limitations. Finally, we present two techniques to test the SIP at the system level: functional system test and embedded component test. Functional system test aims to test the functions of all dies per their specifications at the same time, while embedded component test tries to test each die individually. We conclude the chapter with a brief discussion on future SIP design and test challenges
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lirmm-00195243 , version 1 (10-12-2007)


  • HAL Id : lirmm-00195243 , version 1


Serge Bernard, Philippe Cauvet, Michel Renovell. SIP Test Architectures. Morgan Kaufmann Publishers. System-on-chip Test Architectures: Nanometer Design for Testability, Elsevier, pp.405-441, 2007, 978-0-12-373973-5. ⟨lirmm-00195243⟩
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