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Conference Papers Year : 2001

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Abstract

In this paper we develop a simple and accurate analytical model of the supply current, the output transition time and the delay of inverters designed in submicron technologies. This model considers velocity saturation, load and input ramp effect and also input to output coupling phenomena. Validations are given, on a 0.18μm process, by comparing values of simulated (Hspice) and calculated delay for different configurations of inverters.
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Dates and versions

lirmm-00239444 , version 1 (05-02-2008)

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  • HAL Id : lirmm-00239444 , version 1

Cite

Philippe Maurine, Nadine Azemard, Daniel Auvergne. Full Analyttical Model for delay Performance Estimation in Submicron CMOS. MIXDES: Mixed Design of Integrated Circuits and Systems, Jun 2001, Zakopane, Poland. pp.355-359. ⟨lirmm-00239444⟩
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