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Conference Papers Year : 2001

Delay Bound Determination for Timing Closure Satisfaction

Abstract

Minimizing the number of iterations to satisfy performance constraints when designing complex circuits implies as well a good prediction of the place and route interconnect capacitance than a good knowledge of the feasibility of the constraint imposed on the different circuit parts. We present a method to determine the feasibility of delay constraint imposed on a circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds for delay on combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
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Dates and versions

lirmm-00241322 , version 1 (06-02-2008)

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Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Timing Closure Satisfaction. ISCAS: International Symposium on Circuits and Systems, May 2001, Sydney, NSW, Australia. pp.375-378, ⟨10.1109/ISCAS.2001.922063⟩. ⟨lirmm-00241322⟩
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