Delay Bound Determination for Timing Closure Satisfaction

Abstract : Minimizing the number of iterations to satisfy performance constraints when designing complex circuits implies as well a good prediction of the place and route interconnect capacitance than a good knowledge of the feasibility of the constraint imposed on the different circuit parts. We present a method to determine the feasibility of delay constraint imposed on a circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds for delay on combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
Type de document :
Communication dans un congrès
ISCAS'01: IEEE International Symposium on Circuits and Systems, May 2001, Sydney, Australie, 5, pp.375- 378, 2001
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241322
Contributeur : Nadine Azemard <>
Soumis le : mercredi 6 février 2008 - 11:09:17
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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  • HAL Id : lirmm-00241322, version 1

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Nadine Azemard, Michel Aline, Daniel Auvergne. Delay Bound Determination for Timing Closure Satisfaction. ISCAS'01: IEEE International Symposium on Circuits and Systems, May 2001, Sydney, Australie, 5, pp.375- 378, 2001. 〈lirmm-00241322〉

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