Minimizing the number of iterations to satisfy performance constraints when designing complex circuits implies as well a good prediction of the place and route interconnect capacitance than a good knowledge of the feasibility of the constraint imposed on the different circuit parts. We present a method to determine the feasibility of delay constraint imposed on a circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds for delay on combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.