A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Abstract : Aggressive scaling of transistors is often accompanied by an increase in variability of its intrinsic parameters. In this paper, we point out the importance of considering sensitivity performances due to process variations during SRAM design. We propose a novel dummy bitline driver, an essential component in a self timed merory, which is less sensitive to process variations. A statistical sizing method of this dummy bitline driver is introduced so as to improve the read timing margin, while ensuring a high timing yield. The memory considered is a 253kb SRAM design in 90nm technology node.
Type de document :
Communication dans un congrès
DELTA'08: Fourth IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China, IEEE Computer Society, pp.107-110, 2008, 〈www.ece.ust.hk/delta2008/〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00243966
Contributeur : Martine Peridier <>
Soumis le : jeudi 7 février 2008 - 10:00:01
Dernière modification le : mardi 26 juin 2018 - 01:18:37

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  • HAL Id : lirmm-00243966, version 1

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Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. DELTA'08: Fourth IEEE International Symposium on Electronic Design, Test and Applications, Jan 2008, Hong Kong, China, IEEE Computer Society, pp.107-110, 2008, 〈www.ece.ust.hk/delta2008/〉. 〈lirmm-00243966〉

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