Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Abstract : Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction procedure considering the maximum current available in the serial transistor array. Validation of this modeling is obtained by comparing calculated gate output transition time to simulated ones (HSPICE level and foundry card model on 0.18µm process)
Type de document :
Communication dans un congrès
PATMOS'01: 11th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland, pp.5.3.1-5.3.10, 2001
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00244010
Contributeur : Nadine Azemard <>
Soumis le : jeudi 7 février 2008 - 11:10:59
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

Identifiants

  • HAL Id : lirmm-00244010, version 1

Collections

Citation

Philippe Maurine, Nadine Azemard, Daniel Auvergne. Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination. PATMOS'01: 11th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2001, Yverdon-Les-Bains, Switzerland, pp.5.3.1-5.3.10, 2001. 〈lirmm-00244010〉

Partager

Métriques

Consultations de la notice

35