Designing high performance circuits requires trade-off definition between speed, power and area. Based on a design oriented modeling of the delay, this work presents a method to define metrics allowing to characterize the criticality of nodes. The purpose of this work is to define indicators for the selection of optimization alternatives. The validation of these indicators is obtained through comparison to the critical loads determined from Spice simulations. The application to various benchmarks shows that, without enumeration, an initial path delay improvement can be obtained at reduced area/power cost by just applying this metric to identify the critical nodes that are the best candidates for speed optimization