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A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics

Abstract : With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article aims at comparing a set of representative static flip-flop architectures used in digital designs and at studying their sensitivity to process variations. Clock-to-Q delay, hold time and setup time means and standard deviations are compared for a low power 65nm technology and commented. Then, a study of the hold/setup time failure probabilities according to the flip-flop used in a critical path is given to illustrate their robustness toward process variations.
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Contributor : Martine Peridier <>
Submitted on : Wednesday, July 23, 2008 - 3:23:26 PM
Last modification on : Tuesday, January 12, 2021 - 4:37:59 PM
Long-term archiving on: : Saturday, November 26, 2016 - 12:29:29 AM


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  • HAL Id : lirmm-00305246, version 1


Bettina Rebaud, Marc Belleville, Christian Bernard, Michel Robert, Patrick Maurine, et al.. A Comparative Study of Variability Impact on Static Flip-Flop Timing Characteristics. ICICDT: International Conference on IC Design and Technology, Jun 2008, Grenoble, France. pp.167-170. ⟨lirmm-00305246⟩



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