Power dissipation has become a major design objective in many application areas, such as wireless communications and high performance computing, thus leading to the production of numerous low-power designs. At the same time, power dissipation is also becoming a critical parameter during manufacturing test, as the design can consume much more power during test than during functional mode of operation. Because test throughput and manufacturing yield are often affected by test power, dedicated test methodologies have emerged over the past decade. In this chapter, we discuss issues arising from excessive power consumption during test application as well as provide structural and algorithmic solutions that can be used to alleviate the low-power test problems. We first review some basic elements of power modeling and related terminologies. After discussing test power issues, promising low-power test techniques to deal with nanometer system-on-chip (SOC) designs are presented. These techniques can be broadly classified into those that apply during scan testing and those that apply during built-in self-test (BIST). A few of them are also applicable to test compression circuits or memory designs.