As the interconnect lines play an increasingly dominant role in determining circuit performance, the dynamic delay variation due to the switching activity of neighboring lines has to be accurately characterized. The goal of this work is to simulate the effect of inductance and routing orientation and then to investigate their effects on timing performances by considering three configurations of three parallel coupled interconnects. For a Deep-Sub-Micron process, we show that when analyzing VLSI circuits, if standard distributed RC models are used, and inductive effects and routing orientation are ignored, large errors can occur in the prediction and evaluation of the circuit behaviour. Both affect greatly circuit performances.