A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Domains

Micro and nanotechnologies/Microelectronics

Martine Peridier  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00679513

Submitted on : Thursday, March 15, 2012-5:28:20 PM

Last modification on : Friday, March 24, 2023-2:52:55 PM

No file

Dates and versions

lirmm-00679513 , version 1 (15-03-2012)

Identifiers

  • HAL Id : lirmm-00679513 , version 1

Cite

Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. GDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France. ⟨lirmm-00679513⟩

Export

BibTeX TEI Dublin Core DC Terms EndNote Datacite

Collections

CNRS SYSMIC LIRMM LIRMM_MIC MIC MIPS UNIV-MONTPELLIER EC_LYON_STRICT
98 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More