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Poster communications

tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits

Giorgio Di Natale 1 Marie-Lise Flottes 1 Feng Lu 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents tLIFTING, an open-source fault simulator able to perform both logic and fault simulations for stuck-at faults, Single/Multiple Event Transient (SET/MET), and Single Event Upset (SEU) and Multiple Bit Upset (MBU) on digital circuits described in Verilog. tLIFTING allows delay-annotated simulation and it can deals with Standard Delay Format (SDF) files. It provides several features for accurate selection of fault location, time and period, with extensive log results meaningful for research purposes.
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Poster communications
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Contributor : Bruno Rouzeyre <>
Submitted on : Tuesday, March 12, 2013 - 6:06:45 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Monday, June 17, 2013 - 12:28:00 PM


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  • HAL Id : lirmm-00799892, version 1



Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS'2012: XVII Conference on Design of Circuits and Integrated Systems, Nov 2012, avignon, France. pp.1, 2012. ⟨lirmm-00799892⟩



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