Skip to Main content Skip to Navigation
Conference papers

An IR-Drop Simulation Principle Oriented to Delay Testing

Abstract : This paper deals with delay fault simulation of logic circuits in the context of IR-drop induced delay. An original algorithm is proposed allowing to perform a per-cycle delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
Complete list of metadatas

Cited literature [5 references]  Display  Hide  Download

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00804254
Contributor : Mariane Comte <>
Submitted on : Monday, March 25, 2013 - 11:35:14 AM
Last modification on : Thursday, August 20, 2020 - 12:00:29 PM
Long-term archiving on: : Wednesday, June 26, 2013 - 4:01:41 AM

File

DCIS-2012-camera_ready.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : lirmm-00804254, version 1

Collections

Citation

Marina Aparicio Rodriguez, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell, et al.. An IR-Drop Simulation Principle Oriented to Delay Testing. DCIS'12: 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.404-409. ⟨lirmm-00804254⟩

Share

Metrics

Record views

692

Files downloads

2150