An IR-Drop Simulation Principle Oriented to Delay Testing
Résumé
This paper deals with delay fault simulation of logic circuits in the context of IR-drop induced delay. An original algorithm is proposed allowing to perform a per-cycle delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
Origine : Fichiers produits par l'(les) auteur(s)
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