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Poster communications

A Time-Efficient Simulation Flow for DAC Characterization & Optimization

Abstract : This paper introduces a time-efficient simulation flow for the design of Digital to Analog Converters (DAC). Evaluation of non-linearities in DACs requires intensive Monte-Carlo (MC) simulations to evaluate the impact of manufacturing mismatches. It is proposed to evaluate non-linearities in the DC domain thus limiting simulation to a reasonable time and to optimize the design for non-linearities before evaluating the speed of the converter in the transient domain for a limited set of MC runs. Characterization is based on the development of Verilog-A modules that drives the digital port of the DAC while acquiring and analyzing its analog output.
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Poster communications
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00814994
Contributor : Frédérick Mailly <>
Submitted on : Thursday, April 18, 2013 - 9:45:54 AM
Last modification on : Thursday, March 5, 2020 - 5:55:02 PM

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  • HAL Id : lirmm-00814994, version 1

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Patcharee Kongpark, Laurent Latorre, Frédérick Mailly, Pascal Nouet. A Time-Efficient Simulation Flow for DAC Characterization & Optimization. DCIS'2012: XXVII Conference on Design of Circuits and Integrated Systems, Avignon, France. pp.298-299, 2012. ⟨lirmm-00814994⟩

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