This paper introduces a time-efficient simulation flow for the design of Digital to Analog Converters (DAC). Evaluation of non-linearities in DACs requires intensive Monte-Carlo (MC) simulations to evaluate the impact of manufacturing mismatches. It is proposed to evaluate non-linearities in the DC domain thus limiting simulation to a reasonable time and to optimize the design for non-linearities before evaluating the speed of the converter in the transient domain for a limited set of MC runs. Characterization is based on the development of Verilog-A modules that drives the digital port of the DAC while acquiring and analyzing its analog output.