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Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison

Jean da Rolt 1 Giorgio Di Natale 1, * Marie-Lise Flottes 1 Bruno Rouzeyre 1
* Corresponding author
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Hardware implementation of cryptographic algorithms is 6 subject to various attacks. It has been previously demonstrated that scan 7 chains introduced for hardware testability open a back door to potential 8 attacks. Here, we propose a scan-protection scheme that provides testing 9 facilities both at production time and over the course of the circuit's life. 10 The underlying principles to scan-in both input vectors and expected 11 responses and to compare expected and actual responses within the 12 circuit. Compared to regular scan tests, this technique has no impact 13 on the quality of the test or the model-based fault diagnosis. It entails 14 negligible area overhead and avoids the use of an authentication test 15 mechanism.
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Submitted on : Friday, July 5, 2013 - 12:17:42 PM
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Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951. ⟨10.1109/TVLSI.2013.2257903⟩. ⟨lirmm-00841650⟩



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