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Conference Papers Year : 2015

Embedded test instrument for on-chip phase noise evaluation of analog/IF signals

Abstract

This paper presents an embedded test instrument for on-chip phase noise evaluation of analog/IF signals. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. The module is validated through behavioral and structural simulations. Its implementation in CMOS 140nm technology occupies only 7,885µm2, which represents an extremely small silicon area.
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lirmm-01233136 , version 1 (24-11-2015)

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Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre. Embedded test instrument for on-chip phase noise evaluation of analog/IF signals. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.237-242, ⟨10.1109/DDECS.2015.11⟩. ⟨lirmm-01233136⟩
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