Embedded test instrument for on-chip phase noise evaluation of analog/IF signals

Florence Azaïs 1 Stéphane David-Grignot 2 Laurent Latorre 1 François Lefevre 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents an embedded test instrument for on-chip phase noise evaluation of analog/IF signals. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. The module is validated through behavioral and structural simulations. Its implementation in CMOS 140nm technology occupies only 7,885µm2, which represents an extremely small silicon area.
Type de document :
Communication dans un congrès
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. IEEE, Proc. of the 18th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15), pp.237-242, 2015, 〈10.1109/DDECS.2015.11〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233136
Contributeur : Florence Azais <>
Soumis le : mardi 24 novembre 2015 - 15:24:37
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

Identifiants

Collections

Citation

Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre. Embedded test instrument for on-chip phase noise evaluation of analog/IF signals. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. IEEE, Proc. of the 18th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15), pp.237-242, 2015, 〈10.1109/DDECS.2015.11〉. 〈lirmm-01233136〉

Partager

Métriques

Consultations de la notice

49