Digital on-chip measurement circuit for built-in phase noise testing

Stéphane David-Grignot 1, 2 Florence Azaïs 2 Laurent Latorre 3 François Lefevre 1
2 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a digital on-chip measurement circuit for built-in phase noise evaluation of analog/IF signals. The technique relies on 1-bit acquisition and on-the-fly processing to compute a digital signature related to the phase noise level present in the analog signal. In order to minimize the required hardware resources, the circuit is designed with a semi-pipeline architecture and modular arithmetic. It has been implemented for validation on a FPGA-based platform. Experimental measurements on both a synthesized signal and the IF output of a silicon tuner demonstrate a very good agreement with the conventional external technique.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233161
Contributor : Florence Azais <>
Submitted on : Tuesday, November 24, 2015 - 3:41:37 PM
Last modification on : Wednesday, May 8, 2019 - 2:56:01 PM

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Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre. Digital on-chip measurement circuit for built-in phase noise testing. IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. ⟨10.1109/IMS3TW.2015.7177880⟩. ⟨lirmm-01233161⟩

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