An intra-cell defect grading tool
Résumé
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Mots clés
Test
Intra-cell defect
Fault simulation
Diagnosis
Dictionaries
Logic gates
Databases
continuous scaling
intra-cell defect grading tool
Circuit faults
Automatic test pattern generation
Transistor size
intra-cell diagnosis resolution
Intra-cell defects
scaling circuits
applied test set
integrated circuit testing
flip-flops
Integrated circuit modeling
Libraries
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