An intra-cell defect grading tool

Abstract : With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
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Communication dans un congrès
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.298-301, 2014, 〈10.1109/DDECS.2014.6868814〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248591
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:25
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

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Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi, et al.. An intra-cell defect grading tool. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.298-301, 2014, 〈10.1109/DDECS.2014.6868814〉. 〈lirmm-01248591〉

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