TSV aware timing analysis and diagnosis in paths with multiple TSVs
Résumé
3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.
Mots clés
Integrated circuit testing
3D integration
Through-Silicon vias (TSV)
Multivariate statistics
Fault diagnosis
Integrated circuit modelling
Three-dimensional integrated circuits
Probability density function
Through-silicon vias
Three-dimensional displays
Timingo
3D integrated circuit test
TSV aware timing analysis
TSV fault
Critical path delay
Delay fault coverage
Delay variation
Resistive open TSV
Resistive open defect
Timing aware model
Circuit faults
Correlation
Delays
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