TSV aware timing analysis and diagnosis in paths with multiple TSVs

Abstract : 3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.
Type de document :
Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Apr 2014, Napa, CA, United States. VLSI Test Symposium (VTS), 2014 IEEE 32nd, pp.1-6, 2014, 〈10.1109/VTS.2014.6818772〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248594
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:29
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

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Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. TSV aware timing analysis and diagnosis in paths with multiple TSVs. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Apr 2014, Napa, CA, United States. VLSI Test Symposium (VTS), 2014 IEEE 32nd, pp.1-6, 2014, 〈10.1109/VTS.2014.6818772〉. 〈lirmm-01248594〉

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