Timing-aware ATPG for critical paths with multiple TSVs

Abstract : Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.
Type de document :
Communication dans un congrès
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.116-121, 2014, 〈10.1109/DDECS.2014.6868774〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248600
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:37
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

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Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Timing-aware ATPG for critical paths with multiple TSVs. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.116-121, 2014, 〈10.1109/DDECS.2014.6868774〉. 〈lirmm-01248600〉

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