Timing-aware ATPG for critical paths with multiple TSVs

Carolina Momo Metzler 1 Aida Todri-Sanial 2 Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Arnaud Virazel 1
1 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248600
Contributor : Aida Todri-Sanial <>
Submitted on : Sunday, December 27, 2015 - 9:41:37 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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Carolina Momo Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Timing-aware ATPG for critical paths with multiple TSVs. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.116-121, ⟨10.1109/DDECS.2014.6868774⟩. ⟨lirmm-01248600⟩

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