Timing-aware ATPG for critical paths with multiple TSVs
Abstract
Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.
Keywords
Defective TSVs
Commercial ATPG tools
Multiple TSVs
Path delay variations
Small delay faults
Small delay variations
Statistical delay quality level
Test patterns
Through-silicon-vias
Timing-aware ATPG
Automatic test pattern generation
Circuit faults
SDF detectability
IR-drop
3D-IC reliability
SDQL metric
TSV testing quality
Integrated circuit reliability
Electrical conditions
Integrated circuit testing
Three-dimensional integrated circuits
Small-delay faults
Delays
Three-dimensional displays
3D integration technology
3D integration
Through-Silicon vias
Resistive open defects
Critical paths