An effective hybrid fault-tolerant architecture for pipelined cores

Abstract : Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipelined cores. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies run in parallel while the third one remains in standby until an error is detected. We have implemented this approach on a MIPS microprocessor as case study. Experiments show that our approach is comparable to TMR in terms of area with a notable power saving and offers a full protection against transient and permanent faults.
Type de document :
Communication dans un congrès
ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. Test Symposium (ETS), 2015 20th IEEE European, pp.1-6, 2015, 〈10.1109/ETS.2015.7138733〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730
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Soumis le : mardi 17 mai 2016 - 14:27:56
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard. An effective hybrid fault-tolerant architecture for pipelined cores. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. Test Symposium (ETS), 2015 20th IEEE European, pp.1-6, 2015, 〈10.1109/ETS.2015.7138733〉. 〈lirmm-01272730〉

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