An effective hybrid fault-tolerant architecture for pipelined cores
Abstract
Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipelined cores. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies run in parallel while the third one remains in standby until an error is detected. We have implemented this approach on a MIPS microprocessor as case study. Experiments show that our approach is comparable to TMR in terms of area with a notable power saving and offers a full protection against transient and permanent faults.
Keywords
Fault tolerant systems
CMOS logic circuits
Transient analysis
Registers
Fault tolerance
Redundancy
Microprocessors
Combinational circuits
Logic design
Integrated circuit reliability
Microprocessor chips
CMOS technology scaling
Pipelined cores
MIPS microprocessor
Circuit faults
Pipelines
Transient and permanent faults