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Conference Papers Year : 2016

Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?

Abstract

Network on Chip (NoC) communication infrastruc-tures are increasingly being used in modern manycore architec-tures. Many industrial and research NoC simulators have been proposed in the last years in order to facilitate the design of such communication infrastructures. As any simulator, all of them have to trade off speed and accuracy. Simulation time directly depends on the simulation accuracy. It also directly depends on the complexity of the system to be simulated, e.g., the number of cores and their unit complexity. In this work, we show that the memory footprint of NoC simulators can be a serious factor limiting the simulation of manycore architectures with a large number of cores. We first quantitatively compare the memory footprint of a transactional level modeling NoC simulator and its cycle-accurate counterpart to show that memory footprint is a concern. Then, we show that memory footprint is also largely impacted by the choice of the programming abstraction by comparing two cycle-accurate simulators written using different application programming interfaces, i.e., plain C++ and SystemC.
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Dates and versions

lirmm-01332702 , version 1 (16-06-2016)

Identifiers

  • HAL Id : lirmm-01332702 , version 1

Cite

Manuel Selva, Abdoulaye Gamatié, David Novo, Gilles Sassatelli. Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?. ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2016, Tallinn, Estonia. ⟨lirmm-01332702⟩
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