Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration

Anastasiia Butko 1 Florent Bruguier 1 Abdoulaye Gamatié 1 Gilles Sassatelli 1 David Novo 1 Lionel Torres 1 Michel Robert 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big.LITTLE. These processors offer increased energy efficiency through combining low power in- order cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications. In this paper, we explore the design of those architectures based on the ARM big.LITTLE technology by modeling performance and power in gem5 and McPAT frameworks. Our models are validated w.r.t. the Samsung Exynos 5 Octa (5422) chip. We show average errors of 20% in execution time, 13% for power consumption and 24% for energy-to-solution.
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Contributor : Abdoulaye Gamatié <>
Submitted on : Friday, December 16, 2016 - 11:21:55 PM
Last modification on : Monday, May 13, 2019 - 11:28:34 AM
Long-term archiving on : Monday, March 20, 2017 - 8:35:26 PM

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Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, David Novo, et al.. Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration. MCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩. ⟨lirmm-01418745⟩

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