Improvement of the tolerated raw bit-error rate in NAND Flash-based SSDs with the help of embedded statistics

Valentin Gherman Emna Farjallah Jean-Marc Armani Marcelino Seif Luigi Dilillo 1
1 TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Solid-state drives (SSDs) based on NAND flash memories provide an attractive storage solution as they are faster and less power hungry than traditional hard-disc drives (HDDs). Aggressive storage density improvements in flash memo¬ries enabled reductions of the cost per gigabit but also caused reliability degradations. A recent large-scale study revealed that the uncorrectable bit error rates (UBER) in data center SSDs may fall far below the JEDEC standard recom-mendations. Here, a technique is proposed to improve the tol-erated raw bit error rate (RBER) based on the observation that (a) a small SSD ratio may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. Instead of employing stronger but costly error-correcting codes a statistical approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next read operation is an indication that data needs to be refreshed. It is estimated that the tolerated RBER can be increased by more than a decade over a storage period of 3 years if the stored data is verified on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. This enables performance overhead reductions with factors between 8x and 12x as compared to a conventional scheme with fixed refresh frequency.
Type de document :
Communication dans un congrès
ITC: International Test Conference, Oct 2017, Fort Worth, United States. 48th International Test Conference, 2017, ITC Proceedings. 〈http://www.itctestweek.org/welcome-2017-itc/〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01582185
Contributeur : Luigi Dilillo <>
Soumis le : mardi 5 septembre 2017 - 17:13:09
Dernière modification le : jeudi 11 janvier 2018 - 06:28:13

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  • HAL Id : lirmm-01582185, version 1

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Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo. Improvement of the tolerated raw bit-error rate in NAND Flash-based SSDs with the help of embedded statistics. ITC: International Test Conference, Oct 2017, Fort Worth, United States. 48th International Test Conference, 2017, ITC Proceedings. 〈http://www.itctestweek.org/welcome-2017-itc/〉. 〈lirmm-01582185〉

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