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Conference Papers Year : 2018

Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy

Pierre-Yves Péneau
David Novo
Florent Bruguier
Lionel Torres
Gilles Sassatelli
Abdoulaye Gamatié

Abstract

Modern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known benefits of STT-MRAM are their near-zero static power and high density compared to volatile memories. Nonetheless, their high write latency may be detrimental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache replacement policy. The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up to 10% compared to SRAM cache with LRU on a single core system.
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Dates and versions

lirmm-01669254 , version 1 (22-05-2018)
lirmm-01669254 , version 2 (02-10-2018)

Identifiers

Cite

Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, et al.. Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy. ARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩. ⟨lirmm-01669254v2⟩
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