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Conference papers
Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy
Abstract : Modern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known benefits of STT-MRAM are their near-zero static power and high density compared to volatile memories. Nonetheless, their high write latency may be detrimental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache replacement policy. The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up to 10% compared to SRAM cache with LRU on a single core system.
Cited literature [18 references]
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01669254
Contributor : Pierre-Yves Péneau <>
Submitted on : Tuesday, October 2, 2018 - 11:13:28 AM
Last modification on : Friday, May 8, 2020 - 11:28:03 AM
Document(s) archivé(s) le : Thursday, January 3, 2019 - 1:41:32 PM
Contributor : Pierre-Yves Péneau <>
Submitted on : Tuesday, October 2, 2018 - 11:13:28 AM
Last modification on : Friday, May 8, 2020 - 11:28:03 AM
Document(s) archivé(s) le : Thursday, January 3, 2019 - 1:41:32 PM
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peneau2018improving.pdf
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