Combined analysis of supply voltage and body-bias voltage for energy management

Rida Kheirallah 1 Jean-Marc Galliere 2 Nadine Azemard 3 Gilles Ducharme 4
2 TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : For advanced technology nodes, static consumption of integrated circuits has become a key factor for the microelectronics industry. Circuit energy efficiency is measured in terms of delay performance and consumption. With the increase of physical and environmental parameters, the Fully-Depleted Silicon-on-Insulator technology allows to extend Moore's law in the nanometer domain. In this work, a statistical study of CMOS-FDSOI integrated circuit energy is carried out. Statistical libraries characterizing delay and power of CMOS-FDSOI transistors are presented. Given the advantages of the FDSOI technology, statistical approaches based on the libraries are applied in order to estimate delay and power. Combined analysis of supply voltage and body-bias voltage allows to determine an efficient Delay-Power compromise and to manage circuit energy with a significant gain in CPU time.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01867809
Contributor : Nadine Azemard <>
Submitted on : Tuesday, September 4, 2018 - 4:11:35 PM
Last modification on : Wednesday, April 17, 2019 - 7:58:01 PM

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Rida Kheirallah, Jean-Marc Galliere, Nadine Azemard, Gilles Ducharme. Combined analysis of supply voltage and body-bias voltage for energy management. PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. ⟨10.1109/PATMOS.2018.8464159⟩. ⟨lirmm-01867809⟩

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